1. Technical Field
The present invention relates to a data transmission, and more particularly, to a skew removal circuit and method capable of reducing a skew between data and clock signal.
2. Description
A data transmission speed performed in a data transmission/reception system constructed of semiconductor device, i.e., CPU and semiconductor memory device, is becoming faster day by day according to the requirement of users. However, time jitter of PLL/DLL, offset generated by a process error of transmitter/receiver and a signal interference of transmission channel etc. cause a skew occurrence between data and a clock signal that samples data, thus this becomes the factor of limiting a data transmission speed increase.
In general, when the transmission speed of data becomes increased, voltage margin and time margin of data necessary for identifying bit information of data are more reduced. That is, to exactly identify data transmitted from a transmitting side without error at a receiving side, it is required to precisely place a clock signal to sample data at a position having a relatively largest time margin of data, i.e., center part of data.
For that, a conventional parallel link interface method has been employed a source synchronous scheme. In the source synchronous scheme, transmitting side transmits together with data and clock signal to be sampled to receiving side, and receiving side extracts the data and clock signal. But, in the source synchronous scheme, skew is generated by a mismatch between a data line and a sampling clock line and thus there is caused a limit in a high-speed operation having a very fast transmission speed.
Therefore, a skew removal method employing a clock data recovery (hereinafter, referred to as ‘CDR’) to remove skew between data and a clock signal has been mainly used in the field of serial link interface. In the skew removal method using the CDR, transmission data is oversampled at a receiving side, and a phase of transmission sampling clock of a transmitting side is controlled according to sampled information. Then, clock signal sampling the data (hereinafter, referred to as ‘sampling clock’) is controlled to have a relatively largest time margin for data to be sampled at the receiving side.
FIG. 1 illustrates a signal timing for a correlation between clock signals and data used in the CDR scheme according to a conventional art.
Referring to FIG. 1, two kinds of clock signals are shown for three cases in a lower part of data waveform. An edge clock Clk_edge with a reference character C1 is positioned in timing at an edge portion of 1 bit data, and data clock Clk_data with a reference character C2 is positioned in timing on a center part of the 1 bit data. A time interval between the data clock Clk_data and the edge clock Clk_edge corresponds to a half (0.5 UI) of data bit period UI as T_bit. In the drawing, the data clock Clk_data corresponds to the sampling clock and is a clock signal necessary for identifying data. On the other hand, the edge clock Clk_edge is a clock signal necessary for extracting edge information of data. In the following description, for example, when the edge clock is called a first clock signal, the data clock will be called a second clock signal.
In FIG. 1, for example, when data is changed from logic 0 to logic 1 or from logic 1 to logic 0, an early/late phase correlation between data and sampling clock Clk_data can be obtained by using the edge clock Clk_edge. For example, when the sampling clock Clk_data is positioned in timing after a center part of data bit period as shown in a second case S2 and so the data is delayed or the sampling clock Clk_data is advanced corresponding to a generated skew SKEW1, skew between data and sampling clock is removed and becomes like the first case shown in S1. Meanwhile, to the contrary, when sampling clock is positioned in timing before a center part of data bit period like a third case shown in S3, skew between data and sampling clock can be removed by advancing in timing corresponding to an interval of skew SKEW2 the data or shifting in timing the sampling clock.
Consequently, in the conventional CDR scheme using all of edge clock and data clock as illustrated in FIG. 1, data sampled as edge clock in 1 bit data period and data sampled as data clock can be obtained. Thus, the conventional CDR scheme obtains two information for 1 bit data period and so is called ‘×2 oversampling’ in view of a sampling technique. For example, when the edge clock Clk_edge tracks an edge of data, the data clock Clk_data is shifted 0.5 UI (Unit Interval) from the edge clock, and thus the timing is automatically matched to the center of data eye. Therefore, skew between data and sampling clock is substantially reduced by controlling a phase of sampling clock signal through use of oversampled information.
The conventional CDR scheme may be advantageous by the characteristic that a sampling clock signal tracks a phase change of data and maintains a proper sampling position even during a transmission of data. That is, there is no special operation change even when temperature or voltage is changed.
However, the conventional CDR scheme necessarily requires a specific clock signal, i.e., edge clock Clk_edge, to identify edge information of data. When edge clock is used in addition to sampling clock in the receiving side, power consumption of the receiving side is added corresponding to that. Furthermore, the conventional CDR scheme must additionally include a reception circuit for identifying data and sampling clock and detecting an edge of data, and a phase control circuit for changing a phase of clock signal. The conventional CDR scheme has an overhead for circuits and so its application to the parallel link interface method as an interface method of DRAM etc. is not simple.
As another conventional art, a skew compensation scheme using a training method is known in a parallel link interface used in a DRAM (Dynamic Random Access Memory) etc.
In the skew compensation scheme using the training method, circuits can be realized on a small area as compared with the conventional CDR scheme and a skew removal function of almost the same level as the CDR scheme can be provided. Further, unlike the conventional CDR scheme, a specific circuit for an edge detection of data is not adapted at a receiving side.
The skew compensation scheme using a training method principally used in semiconductor memory devices such as DRAM etc. is described as follows, referring to FIG. 2.
With reference to FIG. 2 illustrating signal timings providing a correlation between clock signals and training data used in the training method, training data showing a 1 bit data period and a plurality of clock signals S1-S5 sequentially phase-shifted corresponding to a unit step are positioned being spaced in a lower part of the data.
In the training method, a phase shift operation is performed mainly in a transmitting side such as a memory controller etc., not in a semiconductor memory device as a receiving side.
In a training mode of the transmitting side, training data is transmitted at a frequency lower than a normal transmission operation of data. Then, the training data is stored in a data receiving part such as the semiconductor memory device etc. The memory controller reads the stored training data in synchronous to each of the plurality of clock signals S1-S5. That is, the training data is individually sampled by the clock signals S1-S5 phase-shifted corresponding to each step.
When a phase of sampling clock signal is changed by a time interval corresponding to 1 bit data period, the memory controller detects a reception error by comparing the transmitted training data with the individually sampled data. In this case, when phase information of sampling clock signals corresponding to sampling data having an error occurrence is detected, a sampling clock signal having a relatively smallest skew occurrence can be extracted. For example, in FIG. 2, when sampling clock signals S1-S4, S12-S15 having a fail F are detected, sampling clock signals S5-S11 having a relatively low probability for error occurrence can be obtained. That is, in FIG. 2, a sampling clock signal S8 with reference number 22 is obtained as a sampling clock signal having a relatively smallest skew.
However, in the skew removal method using the training data described above with reference to FIG. 2, an operating time of training mode is relatively long as compared with the conventional CDR scheme described referring to FIG. 1. Thus, the performance in a normal operation of system becomes fall when the operation of system is performed too frequently. Furthermore, even though a skew is changed by a temperature or voltage change, data must be still sampled as sampling clock signal having a skew occurrence before the training operation is performed. That is, data reception error may be caused.
As described above, in the skew compensation scheme using the training data there is an advantage an area of circuit is relatively small at a data receiving side, but time taken in a skew removal operation is relatively long and operation stability is weakened due to a temperature and voltage change.
Accordingly, some embodiments of the invention provide a semiconductor device capable of realizing circuits of compact size and substantially reducing power consumption.
Some embodiments of the invention provide a data transmission/reception system capable of shortening time to remove or reduce a skew between data and a clock signal as compared with a conventional skew compensation scheme using training data. The system comprises a skew removal circuit for reducing a circuit overhead of a receiving side and relatively lessening time taken in a training operation.
Some embodiments of the invention provide a data transmission/reception system and a skew removal method capable of realizing circuits in a receiving side more simply and so reducing power consumption.
Some embodiments of the invention provide a skew removal circuit capable of reducing a circuit area of a receiving side without employing an oversampling scheme.
Some embodiments of the invention provide a skew removal circuit and a skew removal method thereof, capable of reducing a circuit overhead of a transmitting side even in employing an oversampling scheme.
Some embodiments of the invention provide a skew removal circuit of an oversampling scheme capable of shortening a skew removal operating time in a circuit of a transmitting side.
Some embodiments of the invention provide an improved skew removal circuit capable of producing increase/decrease information data for a removal of skew in a semiconductor memory device.
Some embodiments of the invention provide a skew removal circuit and a skew removal method thereof, capable of solving a dynamic skew problem that a skew between data and clock signal is frequently changed by a temperature or voltage change. The skew removal can be performed in real time in a normal operating section to access data.
According to an embodiment of the invention, a data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal, comprises a skew information extracting unit for obtaining and outputting skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side; and a timing control unit for receiving the skew edge information data through a transmitting side, and comparing its phase with the transmitted data and controlling a timing between transmission data and transmission sampling clock signal applied to a transmission output unit according to the phase comparison result.
In sampling the transmission data as the first clock signal, the transmission sampling clock signal of the transmitting side is traced to the second clock signal, and in sampling the transmission data as the second clock signal, the transmission sampling clock signal of the transmitting side is traced to the first clock signal.
When the first clock signal is an edge clock, the second clock signal is a data clock for a sampling of data.
The training operating mode may be performed when the transmitting side provides a command to the receiving side or may be automatically performed for a time interval that an access operation of data is not performed.
Further, when the skew information extracting unit is adapted in a semiconductor memory device, the timing control unit may be adapted in a memory controller.
In the configuration according to the embodiment of the invention, time taken in a training operation can be relatively reduced, and a circuit adapted in a receiving side can become relatively more simplified and power consumption can be reduced as compared with a conventional clock data recovery circuit. In addition, a dynamic skew problem that a skew between data and clock signal is frequently changed by a temperature or voltage change, can be solved by performing a skew removal for a refresh time period or performing a skew removal by applying a specific command.
According to another embodiment of the invention, a data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal, comprises a skew removal circuit, the skew removal circuit including an increase/decrease information data extracting unit for obtaining increase/decrease information data necessary for a skew removal by individually sampling data transmitted in a training operating mode as the first and second clock signals in a receiving side and by comparing phases from its sampling result, and for outputting the data through a read request of the data; and a control unit for receiving the increase/decrease information data in a transmitting side, and controlling a phase of transmission sampling clock signal applied to a transmission output unit or controlling a timing of transmission data.
The transmission sampling clock signal of the transmitting side is traced to the second clock signal, and when the first clock signal is an edge clock, the second clock signal is a data clock for a sampling of data.
The training operating mode may be performed when the transmitting side provides a command to the receiving side or may be automatically performed for a time interval that an access operation of data is not performed. Further, when the increase/decrease information data extracting unit is adapted in a semiconductor memory device, the phase control unit may be adapted in a memory controller.
As described above, according to some embodiments of the invention, a circuit overhead of transmitting side can be lessened, and a skew removal operating time in a transmitting-side circuit can be shortened. Further, a skew removal is performed in a normal write operating mode or refresh time interval, or the skew removal is performed by using an applied specific command, thereby performing a skew removal operation in real time and furthermore solving a dynamic skew problem that a skew between data and clock signal is changed very often by a temperature or voltage change.